1. Field of the Invention
The present invention relates to a ferroelectric non-volatile memory device including non-destructive reading, transistor type ferroelectric memory cells arranged in a matrix of rows and columns and having a ferroelectrics for each control gate, and a driving method thereof.
2. Description of the Related Art
One such conventional non-destructive reading, ferroelectric non-volatile memory device is an MFMIS (Metal Ferroelectric Metal Insulator Semiconductor)-FET (Field Effect Transistor) 104 as shown in FIG. 13. In the MFMIS-FET 104, an MIS (Metal Insulator Semiconductor) field effect transistor 101 is formed on a semiconductor substrate 100, and a gate electrode (floating gate electrode) 102 on the gate insulator 109 of the transistor 101 is connected in series with a ferroelectric capacitor Cf including a ferroelectric thin film 103 made of for example PZT (PbZrTiO3) or SBT (SrBi2Ta2O9) and an upper electrode 105.
FIG. 14 is an equivalent circuit diagram of the MFMIS-FET 104 shown in FIG. 13. Voltage V applied across the area between the upper electrode 105 of the ferroelectric capacitor Cf and the semiconductor substrate 100 is distributed into distribution voltage Vf=V(Ci/(Ci+Cf)) and distribution voltage Vi=V(Cf/(Ci+Cf)) in inverse proportion to the ratio between the ferroelectric capacitance Cf and the gate capacitance Ci between the gate electrode 102 and the semiconductor 100 and applied to the capacitors Cf and Ci. The ferroelectric thin film 103 is polarized by the distribution voltage Vf=V(Ci/(Ci+Cf)) applied to the ferroelectric capacitor Cf. The threshold voltage for the MIS field effect transistor 101 is changed depending upon the direction of polarization, which changes the resistance across the channel 108 between the source 106 and the drain 107, so that data represented as the polarization of the ferroelectric thin film 103 is read in the terms of change in the drain current value passed across the channel 108.
According to the method, the residual polarization of the ferroelectric thin film 103 is maintained in order to hold the data, in other words, to maintain the on or off state of the MFMIS-FET 104. Therefore, the device is non-volatile and non-destructive reading is allowed, in other words, data is not destroyed at the time of reading.
The voltage Vf=V(Ci/(Ci+Cf)) distributed to the ferroelectric capacitor Cf depends on the coupling ratio (Ci/(Ci+Cf)) between the capacitance Cf of the ferroelectric capacitor and the capacitance Ci of the gate insulator capacitor. In general, the dielectric constant of the ferroelectric thin film 103 is larger than that of the gate insulator 109, and therefore the capacitance Cf of the ferroelectric capacitor is greater than the gate capacitance Ci for the same area. The voltage V applied across the area between the upper electrode 105 and the substrate 100 is mostly distributed as the distribution voltage Vi=V(Cf/(Ci+Cf)) to the gate capacitor Ci, while the ferroelectric capacitor Cf is provided only with low distribution voltage Vf=V(Ci/(Ci+Cf)). When the electric field caused at the ferroelectric thin film by the voltage Vf is not more than the coercive electric field, sufficient polarization inversion is not caused, and therefore the device does not function as a memory.
An MFMIS-FET 110 as shown in FIG. 15 has been suggested in order to distribute a larger share of voltage to the ferroelectric capacitor Cf. In the shown configuration, the area of the gate electrode 102 of the MIS field effect transistor 101 is larger than that of the ferroelectric thin film 103 and the upper electrode 105 of the ferroelectric capacitor Cf. FIG. 16 is an equivalent circuit diagram of FIG. 15. In this configuration, the coupling ratio (Ci/(Ci+Cf)) is large, and therefore the distribution voltage Vf=V(Ci/(Ci+Cf)) applied to the ferroelectric capacitor Cf can be larger. Consequently, the increased distribution voltage Vf reinforces the polarization, so that the polarization holding capability, in other words, the data holding capability improves.
FIG. 17 is a diagram of the configuration of a ferroelectric non-volatile memory device including four memory cells C11, C12, C21, and C22 each identical to the conventional MFMIS-FET described above and shown in FIG. 14 arranged in a matrix of two rows and two columns on a common semiconductor substrate. Note however that in reality the matrix is made of m rows and n columns altogether (m, n: an integer not less than 2). In the conventional circuit configuration shown in FIG. 17, word lines WL1, WL2, . . . , and WLm (not shown) in the horizontal direction in the figure (hereinafter as “the row direction”) are each connected with the upper electrodes of all the MFMIS-FET memory cells in each corresponding row among cells C11, C12, . . . , C1n (not shown), C21, C22, . . . , C2n(not shown), . . . , Cm1 (not shown), . . . , and Cmn (not shown). Meanwhile, bit lines BL1, BL2, . . . , and BLn (not shown) and source lines SL1, SL2 . . . , and SLn (not shown) in the vertical direction in the figure (hereinafter as “the column direction”) are connected with the drains and the sources, respectively of all the MFMIS-FET memory cells in each corresponding column among the cells C11, C21, . . . , Cm1 (not shown), C12, C22, . . . , Cm2 (not shown), . . . , C1n (not shown), . . . , and Cmn (not shown).
The word lines WL1, WL2, . . . , and WLm (not shown), the bit lines BL1, BL2, . . . , and BLn (not shown) and the source lines SL1, SL2, . . . , and SLn (not shown) are selected by a selection circuit that is not shown.
In the conventional circuit configuration described above, at the time of data writing, a word line WLi and a bit line BLj and/or a source line SLj connected to a memory cell Cij to which data is to be written is selected. At the time of data reading, a word line WLi, a bit line BLj, and a source line SLj connected to a cell Cij from which data is to be read are selected. At the time of data erasure, a word line WLi, a bit line BLj, and/or a source line SLj connected to a memory cell Cij from which data is to be erased are selected. The selected word line Wij, bit line BLj, and source line SLj are provided with prescribed voltage, so that data is written, read and erased. The MFMIS-FET in FIG. 16 may be similarly used in place of the conventional MFMIS-FET as shown in FIG. 17.
In the conventional circuit configuration shown in FIG. 17, since the word line WLi is connected in common with all the memory cells in the row, prescribed voltage for writing, reading or erasure is applied at the same time to the cells other than the memory cell selected for the writing, reading, and erasure. The bit line BLj and the source line SLj are similarly connected in common to all the memory cells in the column, and prescribed voltage for writing, reading or erasure is applied to the memory cells other than the memory cell selected for the writing, reading, or erasure. Therefore, the device is encountered with the following disadvantages.
(1) At the time of data writing, when the word line WLi connected to the memory cell Cij to which data is to be written is selected, writing voltage is applied from the word line WLi to all the memory cells connected to the word lines WLi, and data is written in the memory cells. The memory cell for writing cannot be selected.
(2) At the time of data erasure, the word line WLi connected to the memory cell Cij whose data is to be erased is selected, erasure voltage from the word line WLi is applied to all the memory cells connected to the word line WLi and data in the memory cells is rewritten. Therefore, the memory cell cannot be selected.
(3) At the time of data reading, when the bit line BLj and the source line SLj connected to the memory cell Cij from which data is to be read out are selected, and non-selected memory cells connected to the bit line BLj and the source line SLj are in an on state, current is passed between the bit line BLj and the source line SLj through the non-selected cells. This makes it difficult to determine the on/off state of the selected memory cell Cij.
(4) At the time of reading, when voltage is applied to the word line WLi connected to the memory cell Cij from which data is to be read out in order to select the cell, unwanted voltage is applied to non-selected memory cells similarly connected to the word line WLi, and data in the non-selected memory cells is destroyed.
(5) Negative (−) voltage is necessary in addition to positive (+) voltage in order to invert the polarization. In this case, an additional negative voltage generation circuit or negative voltage generation means provided outside the chip is necessary, which increases the chip area or the number of necessary parts.
In order to solve these disadvantages, there is a known method disclosed by JP-A No. 10-64255 (Japanese laid-open patent application) entitled “Method for Writing Data to Single Transistor Type Dielectric Memory.” According to the method disclosed by this document, when voltage V is applied to a selected memory cell at the time of writing, voltage ±V/3 is applied to non-selected memory cells. According to this conventional method, however, the disadvantage (5) cannot be solved, and when voltage continues to be applied to non-selected memory cells in the direction to invert the polarization, the polarization is inverted, which could give rise to eventual re-writing with wrong data.
Another conventional method disclosed by JP-A No. 11-97559 entitled “Ferroelectric Memory Cell, Method for Driving the Same and Memory Device” also suffers from the same problem.
Meanwhile, as described in conjunction with FIGS. 15 and 16, according to the conventional method, in order to distribute necessary distribution voltage Vf to the ferroelectric capacitor Cf, the coupling ratio (Ci/(Ci+Cf)) between the capacitance Cf of the ferroelectric capacitor and the capacitance Ci of the gate insulator capacitor should be increased. One method to increase the ratio may be to increase the thickness of the ferroelectric capacitor Cf and another method may be to reduce the electrode area. According to the former method, the voltage to be distributed to the ferroelectrics increases, but the electric field is reduced for the increase in the film thickness. According to the latter method, it would be extremely difficult to secure a registration margin when contact holes for Al electrode interconnection to the upper electrode of the ferroelectric capacitor are formed. Alternatively, a gate insulating film for the gate insulator capacitor Ci may be reduced in thickness, or the gate area may be increased. The former method can however increase current leakage or lower breakdown voltage. The latter method restricts flexibility in designing the circuit of the data detection MIS field effect transistor 101. This is not preferable in terms of designing and producing the data detection MIS field effect transistor 101.
Japanese Patent No. 2,800,745 and JP-A Nos. 7-202138 and 2000-349251 disclose the following methods suggested to solve the problems. According to the disclosure of these documents, one terminal of a paraelectric capacitor having a paraelectric substance is connected to a floating gate electrode, and the other terminal of the paraelectric capacitor is connected to the drain of a field effect transistor or a semiconductor substrate, so that the coupling ratio (Ci/(Ci+Cf)) is increased without increasing the area of the gate electrode of the MIS field effect transistor.
However, Japanese Patent No. 2,800,745, and JP-A Nos. 7-202138 and 2000-349251 do not disclose how to write, read, and erase data to/from a memory cell independently from the other memory cells. Therefore, these disclosed methods still suffer from the disadvantages (1) to (5) in writing, reading, erasing data to/from a memory cell.
In addition, according to the methods disclosed by these documents, the paraelectric capacitor is formed separately from the MFMIS structure, and therefore additional interconnection must be provided between them. Therefore, a positioning margin therefor is necessary, which would give rise to unwanted increase in the memory cell area.